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| 4-BIT PARALLEL-TO-SERIAL CONVERTER SY10E446 SY100E446 FEATURES s On-chip clock /4 and /8 s Extended 100E VEE range of -4.2V to -5.5V s s s s s s s s 1.6Gb/s typical data rate capability Differential clock and serial inputs VBB output for single-ended use Asynchronous data synchronization Mode select to expand to 8 bits Internal 75K input pulldown resistors Fully compatible with Motorola MC10E/100E446 Available in 28-pin PLCC package DESCRIPTION The SY10/100E446 are integrated 4-bit parallel-toserial data converters. These devices are designed to operate for NRZ data rates of up to a minimum of 1.3Gb/ s. The chips generate a divide-by-4 and a divide-by-8 clock for both 4-bit conversion and a two-chip 8-bit conversion function. The conversion sequence was chosen to convert the parallel data into a serial stream from bit D0 to D3. A serial input is provided to cascade two E446 devices for 8-bit conversion applications. The SYNC input will asynchronously reset the internal clock circuitry. This pin allows the user to reset the internal clock conversion unit and, thus, select the start of the conversion process. The MODE input is used to select the conversion mode of the device. With the MODE input LOW (or open) the device will function as a 4-bit converter. When the mode input is driven HIGH, the internal load clock will change on every eighth clock cycle, thus allowing for an 8-bit conversion scheme using two E446s. When cascaded in an 8-bit conversion scheme, the devices will not operate at the 1.3Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E446. For lower data rate applications, a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates above 500MHz, differential input signals are recommended. For single-ended inputs, the VBB pin is tied to the inverting differential input and bypassed via a 0.01F capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB can also be used to AC couple an input signal. PIN CONFIGURATION MODE NC NC D0 D1 25 24 23 22 21 20 19 D2 D3 CLK CLK VBB VEE SIN SIN SYNC 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 TOP VIEW PLCC J28-1 16 15 14 13 12 NC NC VCC SOUT SOUT VCCO NC VCCO CL/8 VCCO CL/4 CL/4 VCCO CL/8 PIN NAMES Pin SIN, SIN D0 - D3 SOUT, SOUT CLK, CLK CL/4, CL/4 CL/8, CL/8 MODE SYNC VCCO Function Differential Serial Data Input Parallel Data Input Differential Serial Data Output Differential Clock Input Differential 4 Clock Output Differential 8 Clock Output Conversion Mode, 4-bit/8-bit Conversion Synchronizing Input VCC to Output Rev.: C Amendment: /1 1 Issue Date: February, 1998 Micrel SY10E446 SY100E446 BLOCK DIAGRAM SIN SIN D3 0 D 1 CLK Q 0 D2 D 1 CLK Q 0 D1 D 1 CLK Q 0 D0 D 1 CLK Q SOUT SOUT CL/8 MODE CLK CLK DELAY /4 R /8 R CL/4 SYNC VBB CL/4 0 1 CL/8 2 Micrel SY10E446 SY100E446 TRUTH TABLE Mode L H Conversion 4-Bit 8-Bit DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH VOH Parameter Input HIGH Current Min. -- Typ. -- -- -- -- -- 110 110 Max. 150 Min. -- TA = +25C Typ. -- -- -- -- -- 110 110 Max. 150 -- TA = +85C Min. Typ. -- -- -- -- -- 110 127 Max. 150 -670 -830 V -1.38 -1.38 -- -- -1.27 -1.35 -1.26 -1.38 132 132 -- -- -1.25 -1.31 -1.26 -1.38 132 132 -- -- -1.19 -1.26 mA 10E 100E 132 152 -- -- Unit A V -790 -980 -830 -1025 -760 -910 -830 -1025 Condition -- 1 Output HIGH Voltage (SOUT Only) 10E -1020 (SOUT Only) 100E -1025 Output Reference Voltage 10E 100E Power Supply Current VBB IEE NOTE: 1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E and 100E VOH levels. AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol fMAX tPLH tPHL Parameter Max. Conversion Frequency Min. 1.3 Typ. 1.6 Max. Min. -- 1.3 TA = +25C Typ. 1.6 Max. -- TA = +85C Min. 1.3 Typ. 1.6 Max. -- Unit Gb/s NRZ ps 1400 800 1100 800 -400 -400 -250 550 600 300 200 -- 1700 1000 1100 500 1400 800 1100 500 -- -- -- -- -- -- -- -- -200 -200 0 750 800 500 500 400 1400 800 1100 800 -400 -400 -250 550 600 300 200 -- 1700 1100 1400 1100 -- -- -- -- -- -- -- -- 1000 500 800 500 -200 -200 0 750 800 500 500 400 1400 800 1100 800 -400 -400 -250 550 600 300 200 -- 1700 1100 1400 1100 ps -200 -200 0 750 800 500 500 400 -- -- -- ps -- -- -- -- -- ps ps ps 100 200 225 425 350 650 100 200 225 425 350 650 100 200 225 425 350 650 -- -- 20-80% -- -- Condition -- -- Propagation Delay to Output CLK to SOUT 1000 CLK to CL/4 500 CLK to CL/8 800 SYNC to CL/4, CL/8 500 Set-up Time SIN Dn Mode Hold Time SIN Dn Mode Reset Recovery Time Minimum Pulse Width CLK, MR Rise/Fall Time SOUT Other tS tH tRR tPW tr tf 3 Micrel SY10E446 SY100E446 TIMING DIAGRAMS CLK RESET D0 D1 D2 D3 SOUT D0-1 D1-1 D2-1 D3-1 D0-1 D1-1 D0-2 D1-2 D2-2 D3-2 D2-1 D3-1 D0-2 D1-2 D2-2 D3-2 CL/4 CL/8 Timing Diagram A. 4:1 Parallel-to-Serial Conversion 4 Micrel SY10E446 SY100E446 TIMING DIAGRAMS (CONTINUED) CLK RESET D0 D1 D2 D3 D4(D0B) D5(D1B) D0-1 D1-1 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 D0-1 D1-1 D0-2 D1-2 D2-2 D3-2 D4-2 D5-2 D6-2 D7-2 D2-1 D3-1 D4-1 D5-1 D6-1 D7-1 D0-2 D1-2 D6(D2B) D7(D3B) SOUT CL/4 CL/8 Timing Diagram B. 8:1 Parallel-to-Serial Conversion 5 Micrel SY10E446 SY100E446 APPLICATIONS INFORMATION The SY10E/100E446 are integrated 4:1 parallel-to-serial converters. The chips are designed to work with the E445 device to provide both transmission and receiving of a highspeed serial data path. The E446 can convert 4 bits of data into a 1.3Gb/s NRZ data stream. The device features a SYNC input which allows the user to reset the internal clock circuitry and restart the conversion sequence (see Timing Diagram A). Note that SOUT is triggered by negative clock edges. The E446 features a differential serial input and internal divide-by-eight circuitry to facilitate the cascading of two devices to build an 8:1 multiplexer. Figure 1 illustrates the architecture for an 8:1 multiplexer using two E446s (see Timing Diagram B). Notice the serial outputs (SOUT) of the lower order converter feed the serial inputs of the higher order device. This feed through of the serial inputs bounds the upper end of the frequency of operation. The clock-toserial output propagation delay, plus the set-up time of the serial input pins, must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, tPD CLK to SOUT = 1600ps and ts for SIN = -200ps, yields a minimum period of 1400ps or a clock frequency of 700MHz. The clock frequency is somewhat lower than that of a single converter. In order to increase this frequency, it is recommended that the clock edge feeding the E446A be delayed with respect to the E446B, as shown in Figure 2. Perhaps the easiest way to delay the second clock relative to the first is to take advantage of the differential clock inputs of the E446. By connecting the clock for E446A to the complimentary clock input pin, the device will clock a half a clock period after E446B (Figure 2). Utilizing this simple technique will raise the potential conversion frequency up to the maximum 1.3GHz of a stand-alone E446. CLK CLK E446B SOUT SOUT SIN SIN E446A SOUT SOUT SERIAL DATA D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 PARALLEL DATA 1400ps 200ps CLK tPD CLK to SOUT 1600ps Figure 1. Cascaded 8:1 Converter Architecture 6 Micrel SY10E446 SY100E446 APPLICATIONS INFORMATION CLK CLK E446B SOUT SOUT SIN SIN E446A SOUT SOUT SERIAL DATA D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 PARALLEL DATA 1.3GHz 770ps CLKB CLKA tPD CLK to SOUT Figure 2. Extended Frequency 8:1 Converter Architecture PRODUCT ORDERING CODE Ordering Code SY10E446JC SY10E446JCTR SY100E446JC SY100E446JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 7 Micrel SY10E446 SY100E446 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 8 |
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